Methods in com.eu.miscedautils.shell that return FVPModule |
FVPModule |
IPXACTBackBone.buildVerilogModuleFromComponent(ComponentType comp)
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FVPModule |
Vhdl2VlogBAKUP.convertEntity(FVhPEntity dut)
|
FVPModule |
DesignPlayerBackBone.createHierarchy(FVPModule mod,
java.lang.String colonSeparatedInstNames,
java.lang.String new_hier_name,
java.lang.String new_mod_name)
|
FVPModule |
BrigidBackBone.createHierarchy(FVPModule mod,
java.lang.String colonSeparatedInstNames,
java.lang.String new_hier_name,
java.lang.String new_mod_name)
|
FVPModule |
BayaBackBone.createModule(java.lang.String name)
|
FVPModule |
DesignPlayerBackBone.createVerlogModuleFromVhdlEntity(FVhPBase ent)
|
FVPModule |
BrigidBackBone.createVerlogModuleFromVhdlEntity(FVhPBase ent)
|
FVPModule[] |
BayaBackBone.findAllModules()
|
FVPModule |
IPXACTBackBone.findModule(java.lang.String name)
|
FVPModule |
BrigidBackBone.findModule(java.lang.String name)
|
FVPModule[] |
DesignPlayerBackBone.findModules(java.lang.String regexpr)
|
FVPModule[] |
BrigidBackBone.findModules(java.lang.String regexpr)
|
FVPModule[] |
BayaBackBone.findModules(java.lang.String regexpr)
|
FVPModule |
DesignPlayerBackBone.flattenModule(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHier,
boolean stopAtLeaf,
boolean disable_assignment_merge,
boolean flatten_undefined_modules,
boolean remove_unused_nets,
boolean rename_generated_nets)
|
FVPModule |
BrigidBackBone.flattenModule(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHier,
boolean stopAtLeaf,
boolean disable_assignment_merge,
boolean flatten_undefined_modules,
boolean remove_unused_nets,
boolean rename_generated_nets)
|
FVPModule |
BayaBackBone.getCurrentDesign()
|
FVPModule |
BayaBackBone.getCurrentModule()
|
FVPModule |
BayaBackBone.importIPXACTComponent(java.lang.String compdef_ipxact_file)
|
FVPModule |
BayaBackBone.importVerilogFileList(java.lang.String filelist,
java.lang.String excludefilelist,
java.lang.String topmodule,
java.lang.String incdirs,
java.lang.String definedirectives,
boolean sort,
boolean nowildcard,
java.lang.String encryptKey,
java.lang.String privateKeyFile,
java.lang.String publicKeyFile,
java.lang.String keyOwner,
java.lang.String keyName,
java.lang.String encryptAlgo)
|
FVPModule |
BayaBackBone.importVerilogModule(java.lang.String vlogfile,
java.lang.String excludefilelist,
java.lang.String topmodule,
java.lang.String incdirs,
java.lang.String definedirectives,
boolean sort,
boolean nowildcard,
java.lang.String encryptKey,
java.lang.String privateKeyFile,
java.lang.String publicKeyFile,
java.lang.String keyOwner,
java.lang.String keyName,
java.lang.String encryptAlgo)
|
FVPModule |
DesignPlayerBackBone.removeConcurrentAssignments(FVPModule topMod)
|
FVPModule |
BrigidBackBone.removeConcurrentAssignments(FVPModule topMod)
|
FVPModule |
DesignPlayerBackBone.removeHierarchy(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHierarchies,
boolean stopAtLeaf)
|
FVPModule |
BrigidBackBone.removeHierarchy(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHierarchies,
boolean stopAtLeaf)
|
FVPModule |
IPXACTComponent2RTL.traverseComponentType(ComponentType comp)
|
Methods in com.eu.miscedautils.shell with parameters of type FVPModule |
void |
Verilog2Baya.addModuleProcessed(java.lang.String uniquifiedname,
FVPModule mod)
|
ComponentType |
IPXACTBackBone.buildComponentFromVerilogModule(FVPModule dut)
|
java.lang.String |
Verilog2Baya.convertModule(FVPModule mod)
|
void |
DesignPlayerBackBone.convertModuleToSystemC(FVPModule topMod,
java.lang.String outputdir,
boolean two_value_logic,
boolean write_driver_monitor)
|
void |
BrigidBackBone.convertModuleToSystemC(FVPModule topMod,
java.lang.String outputdir,
boolean two_value_logic,
boolean write_driver_monitor)
|
FVPModule |
DesignPlayerBackBone.createHierarchy(FVPModule mod,
java.lang.String colonSeparatedInstNames,
java.lang.String new_hier_name,
java.lang.String new_mod_name)
|
FVPModule |
BrigidBackBone.createHierarchy(FVPModule mod,
java.lang.String colonSeparatedInstNames,
java.lang.String new_hier_name,
java.lang.String new_mod_name)
|
FVPModuleInstance |
BayaBackBone.createInstance(java.lang.String instName,
FVPModule mod)
|
void |
DesignPlayerBackBone.elaborateVerilogModule(FVPModule mod)
|
void |
BrigidBackBone.elaborateVerilogModule(FVPModule mod)
|
FVPObjectHierNameMap[] |
DesignPlayerBackBone.findGateInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
BrigidBackBone.findGateInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
DesignPlayerBackBone.findInstancesOfModule(java.lang.String modName,
FVPModule startingModule,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
BrigidBackBone.findInstancesOfModule(java.lang.String modName,
FVPModule startingModule,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
DesignPlayerBackBone.findModuleInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
BrigidBackBone.findModuleInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
DesignPlayerBackBone.findUDPInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
BrigidBackBone.findUDPInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
DesignPlayerBackBone.findVerilogModuleNets(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
BrigidBackBone.findVerilogModuleNets(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
DesignPlayerBackBone.findVerilogModulePorts(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
BrigidBackBone.findVerilogModulePorts(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPModule |
DesignPlayerBackBone.flattenModule(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHier,
boolean stopAtLeaf,
boolean disable_assignment_merge,
boolean flatten_undefined_modules,
boolean remove_unused_nets,
boolean rename_generated_nets)
|
FVPModule |
BrigidBackBone.flattenModule(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHier,
boolean stopAtLeaf,
boolean disable_assignment_merge,
boolean flatten_undefined_modules,
boolean remove_unused_nets,
boolean rename_generated_nets)
|
void |
DesignPlayerBackBone.generateVerilogTestbench(FVPModule mod,
java.lang.String outfile)
|
void |
BrigidBackBone.generateVerilogTestbench(FVPModule mod,
java.lang.String outfile)
|
void |
DesignPlayerBackBone.linkVerilogModule(FVPModule mod)
|
void |
BrigidBackBone.linkVerilogModule(FVPModule mod)
|
FVPModule |
DesignPlayerBackBone.removeConcurrentAssignments(FVPModule topMod)
|
FVPModule |
BrigidBackBone.removeConcurrentAssignments(FVPModule topMod)
|
FVPModule |
DesignPlayerBackBone.removeHierarchy(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHierarchies,
boolean stopAtLeaf)
|
FVPModule |
BrigidBackBone.removeHierarchy(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHierarchies,
boolean stopAtLeaf)
|
void |
BayaBackBone.setCurrentModule(FVPModule mod)
|
void |
Verilog2Baya.setObjectProcessed(java.lang.String uniquifiedname,
FVPModule mod)
|
Methods in com.eu.miscedautils.verilogparser that return FVPModule |
FVPModule |
FVPCreateHierarchy.createHierarchy(FVPModule parent,
java.util.LinkedList<java.lang.String> instances,
java.lang.String instanceName,
java.lang.String moduleName)
|
FVPModule |
FVPModule.createHierarchy(java.util.LinkedList<java.lang.String> instances,
java.lang.String newInstName,
java.lang.String newModName)
|
static FVPModule[] |
FindNetsOrInstances.findModules(java.lang.String regexpr)
|
FVPModule |
FVPRemoveHierarchy.flatten()
|
FVPModule |
FVPRemoveHierarchy.flattenModule(FVPModule mod,
FVPModuleInstance modInst,
boolean isTop)
|
FVPModule |
FVPModuleInstance.getMaster()
|
FVPModule |
FVPCreateHierarchy.getNewScope()
|
FVPModule |
FVPRemoveHierarchy.getTopModule()
|
FVPModule |
FVPRemoveAssignments.getTopModule()
|
FVPModule |
FVPModuleInstance.link()
|
FVPModule |
FVPModuleInstance.passParamValuesToMasterAndElaborate()
|
FVPModule |
FVPModule.removeHierarchy(java.lang.String instName,
boolean removeAllHierarchies,
boolean stopAtLeaf,
boolean uniquifyNets,
boolean rename_nets)
|
FVPModule |
FVPModuleInstance.revertParamValuesToMasterAndElaborate()
|
static FVPModule |
FVPUtils.splitIntoBits(FVPModule mod)
|
Methods in com.eu.miscedautils.verilogparser with parameters of type FVPModule |
void |
FVPRoot.addModule(FVPModule mod)
|
void |
FVPModule.addParent(FVPModule mod)
|
void |
FVPUDP.addParent(FVPModule mod)
|
FVPModule |
FVPCreateHierarchy.createHierarchy(FVPModule parent,
java.util.LinkedList<java.lang.String> instances,
java.lang.String instanceName,
java.lang.String moduleName)
|
static FVPObjectHierNameMap[] |
FindNetsOrInstances.findGateInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
static FVPObjectHierNameMap[] |
FindNetsOrInstances.findInstancesOfModule(java.lang.String modName,
FVPModule top,
java.lang.String regexpr,
boolean isHier)
|
static FVPObjectHierNameMap[] |
FindNetsOrInstances.findModuleInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
static FVPObjectHierNameMap[] |
FindNetsOrInstances.findNets(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
static FVPObjectHierNameMap[] |
FindNetsOrInstances.findPorts(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
static FVPObjectHierNameMap[] |
FindNetsOrInstances.findUDPInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPModule |
FVPRemoveHierarchy.flattenModule(FVPModule mod,
FVPModuleInstance modInst,
boolean isTop)
|
java.util.LinkedList<FVPBase> |
FVPRemoveAssignments.getDeletableDeclarations(FVPModule mod)
|
java.util.LinkedList<FVPBase> |
FVPRemoveAssignments.getDeletableObjects(FVPModule mod)
|
boolean |
FVPRemoveAssignments.isModuleAlreadyProcessed(FVPModule mod)
|
void |
FVPRemoveAssignments.markModuleAsProcessed(FVPModule mod)
|
static void |
FVPUtils.mergeActualsInOutputPortMap(FVPModule mod)
|
static void |
FVPUtils.mergeActualsInPortMap(FVPModule mod)
|
static void |
FVPUtils.mergeAssignments(FVPModule mod)
|
java.lang.String |
FVPModuleInstance.printWrapperModuleWithUpdatedParameterValues(java.lang.String wrappername,
FVPModule mod)
|
static java.util.LinkedList<FVPObjectHierNameMap> |
FindNetsOrInstances.processModule(FVPModule mod,
FVPBase.ObjType objtype,
boolean isHier)
|
void |
FVPRoot.removeModule(FVPModule mod)
|
void |
FVPModule.removeParent(FVPModule mod)
|
void |
FVPUDP.removeParent(FVPModule mod)
|
java.util.LinkedList<FVPBase> |
FVPRemoveAssignments.removeUnusedObjects(FVPModule mod)
|
void |
FVPRemoveHierarchy.renameNets(FVPModule module)
|
void |
FVPRemoveAssignments.setDeletableDeclarations(FVPModule mod,
java.util.LinkedList<FVPBase> declList)
|
void |
FVPModuleInstance.setMaster(FVPModule m)
|
void |
FVPCreateHierarchy.setNewScope(FVPModule newScope)
|
void |
FVPRemoveHierarchy.setTopModule(FVPModule topModule)
|
void |
FVPRemoveAssignments.setTopModule(FVPModule topModule)
|
static void |
FVPUtils.splitAllConcatenationInConcurrentAssignmentStatement(FVPModule mod)
|
static void |
FVPUtils.splitAllConcurrentAssignmentStatements(FVPModule mod)
|
static void |
FVPUtils.splitAllInstancePortMaps(FVPModule mod)
|
static void |
FVPUtils.splitConcatenationInAllInstancePortMaps(FVPModule mod)
|
static FVPModule |
FVPUtils.splitIntoBits(FVPModule mod)
|
void |
FVPRemoveAssignments.traverseModule(FVPModule mod)
|