com.eu.miscedautils.shell
Class BrigidBackBone

java.lang.Object
  extended by com.eu.miscedautils.shell.BrigidBackBone

public class BrigidBackBone
extends java.lang.Object


Constructor Summary
BrigidBackBone()
           
 
Method Summary
 void convertModuleToSystemC(FVPModule topMod, java.lang.String outputdir, boolean two_value_logic, boolean write_driver_monitor)
           
 FVPModule createHierarchy(FVPModule mod, java.lang.String colonSeparatedInstNames, java.lang.String new_hier_name, java.lang.String new_mod_name)
           
 FVPModule createVerlogModuleFromVhdlEntity(FVhPBase ent)
           
 void elaborateVerilogModule(FVPModule mod)
           
 FVhPArchitecture findArchitecture(java.lang.String entity, java.lang.String arch, java.lang.String worklib, java.lang.String libraryMapFile)
           
 java.lang.String[] findClockResetTree(java.lang.String modname, java.lang.String clkRstRoot, java.lang.String bufferPattern, java.lang.String nonBufferCellPattern, boolean ignoreWires, boolean matchExactNetName, boolean noFormat)
           
 java.util.LinkedList<java.lang.String> findClockResetTreeFromObjects(FVPBase net, java.util.LinkedList<java.lang.String> transparentCellPatternList, java.util.LinkedList<java.lang.String> nonBufferCellPatternList, boolean ignoreWire)
           
 FVhPConfigurationDeclaration findConfiguration(java.lang.String config, java.lang.String worklib, java.lang.String libraryMapFile)
           
 FVhPEntity findEntity(java.lang.String duname, java.lang.String worklib, java.lang.String libraryMapFile)
           
 FVPObjectHierNameMap[] findGateInstances(FVPModule mod, java.lang.String regexpr, boolean isHier)
           
 FVPObjectHierNameMap[] findInstancesOfModule(java.lang.String modName, FVPModule startingModule, java.lang.String regexpr, boolean isHier)
           
 FVPModule findModule(java.lang.String name)
           
 FVPObjectHierNameMap[] findModuleInstances(FVPModule mod, java.lang.String regexpr, boolean isHier)
           
 FVPModule[] findModules(java.lang.String regexpr)
           
 FVhPPackage findPackage(java.lang.String pack, java.lang.String worklib, java.lang.String libraryMapFile)
           
 FVhPPackageBody findPackageBody(java.lang.String packbody, java.lang.String worklib, java.lang.String libraryMapFile)
           
 FVPObjectHierNameMap[] findUDPInstances(FVPModule mod, java.lang.String regexpr, boolean isHier)
           
 FVPObjectHierNameMap[] findVerilogModuleNets(FVPModule mod, java.lang.String regexpr, boolean isHier)
           
 FVPObjectHierNameMap[] findVerilogModulePorts(FVPModule mod, java.lang.String regexpr, boolean isHier)
           
 FVPModule flattenModule(FVPModule topMod, java.lang.String hierDelimeter, boolean removeAllHier, boolean stopAtLeaf, boolean disable_assignment_merge, boolean flatten_undefined_modules, boolean remove_unused_nets, boolean rename_generated_nets)
           
 void generateVerilogTestbench(FVPModule mod, java.lang.String outfile)
           
 FVhPBase generateVhdlTestbench(FVhPBase entity, java.lang.String outfile)
           
 void geterateKeyFiles(java.lang.String pvtKeyFile, java.lang.String pubKeyFile, java.lang.String algo)
           
 java.lang.String getFile()
           
 java.lang.Integer getLine()
           
 tcl.lang.Interp getTclInterpreter()
           
 FVPDescription getVerilogDescription()
           
 FVhPDescription getVhdlDescription()
           
static BrigidBackBone instance()
           
static BrigidBackBone instance(boolean printBanner)
           
 void linkVerilogModule(FVPModule mod)
           
 FVhPBase loadVhdlDesignUnit(java.lang.String duname, java.lang.String worklib, java.lang.String libraryMapFile)
           
 void parseMixedHDLFileList(java.lang.String infileList, java.lang.String excludefilelist, java.lang.String incdirs, java.lang.String definedirs, boolean nowildcard)
           
 FVPRoot readVerilogFile(java.lang.String vlogfile, java.lang.String excludefilelist, java.lang.String incdirs, java.lang.String definedirs, boolean sort, boolean nowildcard, java.lang.String encryptKey, java.lang.String privateKeyFile, java.lang.String publicKeyFile, java.lang.String keyOwner, java.lang.String keyName, java.lang.String encryptAlgo)
           
 FVPRoot readVerilogFileList(java.lang.String filelist, java.lang.String excludefilelist, java.lang.String incdirs, java.lang.String definedirs, boolean sort, boolean nowildcard, java.lang.String encryptKey, java.lang.String privateKeyFile, java.lang.String publicKeyFile, java.lang.String keyOwner, java.lang.String keyName, java.lang.String encryptAlgo)
           
 FVhPRoot readVhdlFile(java.lang.String infile, java.lang.String worklib, java.lang.String mapfile, java.lang.String excludefilelist, boolean nowildcard)
           
 FVhPRoot readVhdlFileList(java.lang.String filelist, java.lang.String worklib, java.lang.String mapfile, java.lang.String excludefilelist, boolean nowildcard)
           
 FVPModule removeConcurrentAssignments(FVPModule topMod)
           
 FVPModule removeHierarchy(FVPModule topMod, java.lang.String hierDelimeter, boolean removeAllHierarchies, boolean stopAtLeaf)
           
 void reset()
           
 void setFile(java.lang.String file)
           
 void setInstance(BrigidBackBone bb)
           
 void setLibraryMappings(java.lang.String worklib, java.lang.String libraryMapFile)
           
 void setLine(java.lang.Integer line)
           
 void setTclInterpreter(tcl.lang.Interp tclInterpreter)
           
 void setVerilogDescription(FVPDescription desc)
           
 void setVhdlDescription(FVhPDescription desc)
           
 
Methods inherited from class java.lang.Object
equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait
 

Constructor Detail

BrigidBackBone

public BrigidBackBone()
Method Detail

reset

public void reset()

instance

public static BrigidBackBone instance(boolean printBanner)

instance

public static BrigidBackBone instance()

setInstance

public void setInstance(BrigidBackBone bb)

getTclInterpreter

public tcl.lang.Interp getTclInterpreter()

setTclInterpreter

public void setTclInterpreter(tcl.lang.Interp tclInterpreter)

getLine

public java.lang.Integer getLine()
Returns:
the line

setLine

public void setLine(java.lang.Integer line)
Parameters:
line - the line to set

getFile

public java.lang.String getFile()
Returns:
the file

setFile

public void setFile(java.lang.String file)
Parameters:
file - the file to set

getVerilogDescription

public FVPDescription getVerilogDescription()

setVerilogDescription

public void setVerilogDescription(FVPDescription desc)

getVhdlDescription

public FVhPDescription getVhdlDescription()

setVhdlDescription

public void setVhdlDescription(FVhPDescription desc)

readVerilogFileList

public FVPRoot readVerilogFileList(java.lang.String filelist,
                                   java.lang.String excludefilelist,
                                   java.lang.String incdirs,
                                   java.lang.String definedirs,
                                   boolean sort,
                                   boolean nowildcard,
                                   java.lang.String encryptKey,
                                   java.lang.String privateKeyFile,
                                   java.lang.String publicKeyFile,
                                   java.lang.String keyOwner,
                                   java.lang.String keyName,
                                   java.lang.String encryptAlgo)
Parameters:
filelist - The name of the file where all the files are listed with full path or proper relative path from the run directory. Example: infile.list
excludefilelist - The name of the file containing list of files to be excluded
incdirs - The list of directories where to search for the included files. Example: +incdir+dir1+dir2
definedirs - The list of directives which needs to considered as defined. Example: +define+macro1+directive2
sort - boolean switch to specify if the file needs to be sorted before parsing Example: true
nowildcard - boolean switch to disable wildcard processing in file name(s) Example: true
encryptAlgo -
Returns:
FVPRoot Returns the Verilog object model root

readVerilogFile

public FVPRoot readVerilogFile(java.lang.String vlogfile,
                               java.lang.String excludefilelist,
                               java.lang.String incdirs,
                               java.lang.String definedirs,
                               boolean sort,
                               boolean nowildcard,
                               java.lang.String encryptKey,
                               java.lang.String privateKeyFile,
                               java.lang.String publicKeyFile,
                               java.lang.String keyOwner,
                               java.lang.String keyName,
                               java.lang.String encryptAlgo)

readVhdlFileList

public FVhPRoot readVhdlFileList(java.lang.String filelist,
                                 java.lang.String worklib,
                                 java.lang.String mapfile,
                                 java.lang.String excludefilelist,
                                 boolean nowildcard)

readVhdlFile

public FVhPRoot readVhdlFile(java.lang.String infile,
                             java.lang.String worklib,
                             java.lang.String mapfile,
                             java.lang.String excludefilelist,
                             boolean nowildcard)

parseMixedHDLFileList

public void parseMixedHDLFileList(java.lang.String infileList,
                                  java.lang.String excludefilelist,
                                  java.lang.String incdirs,
                                  java.lang.String definedirs,
                                  boolean nowildcard)

setLibraryMappings

public void setLibraryMappings(java.lang.String worklib,
                               java.lang.String libraryMapFile)

loadVhdlDesignUnit

public FVhPBase loadVhdlDesignUnit(java.lang.String duname,
                                   java.lang.String worklib,
                                   java.lang.String libraryMapFile)

findEntity

public FVhPEntity findEntity(java.lang.String duname,
                             java.lang.String worklib,
                             java.lang.String libraryMapFile)

findArchitecture

public FVhPArchitecture findArchitecture(java.lang.String entity,
                                         java.lang.String arch,
                                         java.lang.String worklib,
                                         java.lang.String libraryMapFile)

findConfiguration

public FVhPConfigurationDeclaration findConfiguration(java.lang.String config,
                                                      java.lang.String worklib,
                                                      java.lang.String libraryMapFile)

findPackage

public FVhPPackage findPackage(java.lang.String pack,
                               java.lang.String worklib,
                               java.lang.String libraryMapFile)

findPackageBody

public FVhPPackageBody findPackageBody(java.lang.String packbody,
                                       java.lang.String worklib,
                                       java.lang.String libraryMapFile)

generateVhdlTestbench

public FVhPBase generateVhdlTestbench(FVhPBase entity,
                                      java.lang.String outfile)

createVerlogModuleFromVhdlEntity

public FVPModule createVerlogModuleFromVhdlEntity(FVhPBase ent)

generateVerilogTestbench

public void generateVerilogTestbench(FVPModule mod,
                                     java.lang.String outfile)

convertModuleToSystemC

public void convertModuleToSystemC(FVPModule topMod,
                                   java.lang.String outputdir,
                                   boolean two_value_logic,
                                   boolean write_driver_monitor)

linkVerilogModule

public void linkVerilogModule(FVPModule mod)

elaborateVerilogModule

public void elaborateVerilogModule(FVPModule mod)

createHierarchy

public FVPModule createHierarchy(FVPModule mod,
                                 java.lang.String colonSeparatedInstNames,
                                 java.lang.String new_hier_name,
                                 java.lang.String new_mod_name)

findVerilogModuleNets

public FVPObjectHierNameMap[] findVerilogModuleNets(FVPModule mod,
                                                    java.lang.String regexpr,
                                                    boolean isHier)

findVerilogModulePorts

public FVPObjectHierNameMap[] findVerilogModulePorts(FVPModule mod,
                                                     java.lang.String regexpr,
                                                     boolean isHier)

findModuleInstances

public FVPObjectHierNameMap[] findModuleInstances(FVPModule mod,
                                                  java.lang.String regexpr,
                                                  boolean isHier)

findInstancesOfModule

public FVPObjectHierNameMap[] findInstancesOfModule(java.lang.String modName,
                                                    FVPModule startingModule,
                                                    java.lang.String regexpr,
                                                    boolean isHier)

findGateInstances

public FVPObjectHierNameMap[] findGateInstances(FVPModule mod,
                                                java.lang.String regexpr,
                                                boolean isHier)

findUDPInstances

public FVPObjectHierNameMap[] findUDPInstances(FVPModule mod,
                                               java.lang.String regexpr,
                                               boolean isHier)

findModules

public FVPModule[] findModules(java.lang.String regexpr)

findModule

public FVPModule findModule(java.lang.String name)

flattenModule

public FVPModule flattenModule(FVPModule topMod,
                               java.lang.String hierDelimeter,
                               boolean removeAllHier,
                               boolean stopAtLeaf,
                               boolean disable_assignment_merge,
                               boolean flatten_undefined_modules,
                               boolean remove_unused_nets,
                               boolean rename_generated_nets)

removeConcurrentAssignments

public FVPModule removeConcurrentAssignments(FVPModule topMod)

removeHierarchy

public FVPModule removeHierarchy(FVPModule topMod,
                                 java.lang.String hierDelimeter,
                                 boolean removeAllHierarchies,
                                 boolean stopAtLeaf)

geterateKeyFiles

public void geterateKeyFiles(java.lang.String pvtKeyFile,
                             java.lang.String pubKeyFile,
                             java.lang.String algo)

findClockResetTreeFromObjects

public java.util.LinkedList<java.lang.String> findClockResetTreeFromObjects(FVPBase net,
                                                                            java.util.LinkedList<java.lang.String> transparentCellPatternList,
                                                                            java.util.LinkedList<java.lang.String> nonBufferCellPatternList,
                                                                            boolean ignoreWire)

findClockResetTree

public java.lang.String[] findClockResetTree(java.lang.String modname,
                                             java.lang.String clkRstRoot,
                                             java.lang.String bufferPattern,
                                             java.lang.String nonBufferCellPattern,
                                             boolean ignoreWires,
                                             boolean matchExactNetName,
                                             boolean noFormat)