com.eu.miscedautils.shell
Class DesignPlayerBackBone
java.lang.Object
com.eu.miscedautils.shell.DesignPlayerBackBone
public class DesignPlayerBackBone
- extends java.lang.Object
Method Summary |
void |
convertModuleToSystemC(FVPModule topMod,
java.lang.String outputdir,
boolean two_value_logic,
boolean write_driver_monitor)
|
FVPModule |
createHierarchy(FVPModule mod,
java.lang.String colonSeparatedInstNames,
java.lang.String new_hier_name,
java.lang.String new_mod_name)
|
FVPModule |
createVerlogModuleFromVhdlEntity(FVhPBase ent)
|
void |
elaborateVerilogModule(FVPModule mod)
|
void |
executeTclCommand(java.lang.String cmd)
|
FVPObjectHierNameMap[] |
findGateInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
findInstancesOfModule(java.lang.String modName,
FVPModule startingModule,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
findModuleInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPModule[] |
findModules(java.lang.String regexpr)
|
FVPObjectHierNameMap[] |
findUDPInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
findVerilogModuleNets(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPObjectHierNameMap[] |
findVerilogModulePorts(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
|
FVPModule |
flattenModule(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHier,
boolean stopAtLeaf,
boolean disable_assignment_merge,
boolean flatten_undefined_modules,
boolean remove_unused_nets,
boolean rename_generated_nets)
|
void |
generateVerilogTestbench(FVPModule mod,
java.lang.String outfile)
|
FVhPBase |
generateVhdlTestbench(FVhPBase entity,
java.lang.String outfile)
|
BayaBackBone |
getBayaRoot()
|
BrigidBackBone |
getBrigidRoot()
|
void |
geterateKeyFiles(java.lang.String pvtKeyFile,
java.lang.String pubKeyFile,
java.lang.String algo)
|
IPXACTBackBone |
getIPXACTRoot()
|
tcl.lang.Interp |
getTclInterpreter()
|
static DesignPlayerBackBone |
instance()
|
void |
linkVerilogModule(FVPModule mod)
|
FVhPBase |
loadVhdlDesignUnit(java.lang.String duname,
java.lang.String worklib,
java.lang.String libraryMapFile)
|
FVPRoot |
readVerilogFile(java.lang.String vlogfile,
java.lang.String incdirs,
java.lang.String definedirs)
|
FVPRoot |
readVerilogFileList(java.lang.String filelist,
java.lang.String incdirs,
java.lang.String definedirs,
boolean sort)
|
void |
readVhdlFile(java.lang.String fName,
java.lang.String worklib,
java.lang.String mapfile)
|
FVPModule |
removeConcurrentAssignments(FVPModule topMod)
|
FVPModule |
removeHierarchy(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHierarchies,
boolean stopAtLeaf)
|
void |
setBayaRoot(BayaBackBone baya)
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void |
setBrigidRoot(BrigidBackBone brigid)
|
void |
setInstance(DesignPlayerBackBone bb)
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void |
setIPXACTRoot(IPXACTBackBone ipxact)
|
void |
setTclInterpreter(tcl.lang.Interp tclInterpreter)
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Methods inherited from class java.lang.Object |
equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait |
baya
public BayaBackBone baya
ipxact
public IPXACTBackBone ipxact
brigid
public BrigidBackBone brigid
DesignPlayerBackBone
public DesignPlayerBackBone()
instance
public static DesignPlayerBackBone instance()
setInstance
public void setInstance(DesignPlayerBackBone bb)
executeTclCommand
public void executeTclCommand(java.lang.String cmd)
getBayaRoot
public BayaBackBone getBayaRoot()
setBayaRoot
public void setBayaRoot(BayaBackBone baya)
getIPXACTRoot
public IPXACTBackBone getIPXACTRoot()
setIPXACTRoot
public void setIPXACTRoot(IPXACTBackBone ipxact)
getBrigidRoot
public BrigidBackBone getBrigidRoot()
setBrigidRoot
public void setBrigidRoot(BrigidBackBone brigid)
getTclInterpreter
public tcl.lang.Interp getTclInterpreter()
setTclInterpreter
public void setTclInterpreter(tcl.lang.Interp tclInterpreter)
readVerilogFileList
public FVPRoot readVerilogFileList(java.lang.String filelist,
java.lang.String incdirs,
java.lang.String definedirs,
boolean sort)
- Parameters:
filelist
- The name of the file where all the files are
listed with full path or proper relative path
from the run directory. Example: infile.listincdirs
- The list of directories where to search for
the included files. Example: +incdir+dir1+dir2definedirs
- The list of directives which needs to considered as defined.
Example: +define+macro1+directive2sort
- boolean switch to specify if the file needs to be sorted before parsing
Example: true
- Returns:
- FVPRoot Returns the Verilog object model root
readVerilogFile
public FVPRoot readVerilogFile(java.lang.String vlogfile,
java.lang.String incdirs,
java.lang.String definedirs)
readVhdlFile
public void readVhdlFile(java.lang.String fName,
java.lang.String worklib,
java.lang.String mapfile)
loadVhdlDesignUnit
public FVhPBase loadVhdlDesignUnit(java.lang.String duname,
java.lang.String worklib,
java.lang.String libraryMapFile)
generateVhdlTestbench
public FVhPBase generateVhdlTestbench(FVhPBase entity,
java.lang.String outfile)
createVerlogModuleFromVhdlEntity
public FVPModule createVerlogModuleFromVhdlEntity(FVhPBase ent)
generateVerilogTestbench
public void generateVerilogTestbench(FVPModule mod,
java.lang.String outfile)
convertModuleToSystemC
public void convertModuleToSystemC(FVPModule topMod,
java.lang.String outputdir,
boolean two_value_logic,
boolean write_driver_monitor)
linkVerilogModule
public void linkVerilogModule(FVPModule mod)
elaborateVerilogModule
public void elaborateVerilogModule(FVPModule mod)
createHierarchy
public FVPModule createHierarchy(FVPModule mod,
java.lang.String colonSeparatedInstNames,
java.lang.String new_hier_name,
java.lang.String new_mod_name)
findVerilogModuleNets
public FVPObjectHierNameMap[] findVerilogModuleNets(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
findVerilogModulePorts
public FVPObjectHierNameMap[] findVerilogModulePorts(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
findModuleInstances
public FVPObjectHierNameMap[] findModuleInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
findInstancesOfModule
public FVPObjectHierNameMap[] findInstancesOfModule(java.lang.String modName,
FVPModule startingModule,
java.lang.String regexpr,
boolean isHier)
findGateInstances
public FVPObjectHierNameMap[] findGateInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
findUDPInstances
public FVPObjectHierNameMap[] findUDPInstances(FVPModule mod,
java.lang.String regexpr,
boolean isHier)
findModules
public FVPModule[] findModules(java.lang.String regexpr)
flattenModule
public FVPModule flattenModule(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHier,
boolean stopAtLeaf,
boolean disable_assignment_merge,
boolean flatten_undefined_modules,
boolean remove_unused_nets,
boolean rename_generated_nets)
removeConcurrentAssignments
public FVPModule removeConcurrentAssignments(FVPModule topMod)
removeHierarchy
public FVPModule removeHierarchy(FVPModule topMod,
java.lang.String hierDelimeter,
boolean removeAllHierarchies,
boolean stopAtLeaf)
geterateKeyFiles
public void geterateKeyFiles(java.lang.String pvtKeyFile,
java.lang.String pubKeyFile,
java.lang.String algo)